A manufacturing process of a semiconductor device includes, for example, an impurity implantation process to a semiconductor substrate, a film deposition process, a lithography process of transferring a mask pattern to a photoresist, an etching process of processing a thin film deposited by using the mask pattern as an etching mask, a rinsing process, and others.
In the etching process, a dry etching technique is indispensable in order to form a fine pattern.
The semiconductor device is configured of a plurality of MISFETs (Metal Insulator Semiconductor Field Effect Transistors). Each MISFET has a source region, a drain region and agate electrode, and the dry etching technique is used in order to form the gate electrode. For example, the gate electrode is formed by forming a resist mask having a desired mask pattern on a polysilicon film formed on a surface of the semiconductor substrate through a gate insulating film such as an oxide film in a lithography process, and dry-etching the polysilicon film of a part exposed from the resist mask.
In the dry etching process, a technique of controlling a processing dimension of the gate electrode, or a technique of detecting an end point of the dry etching in order to reduce an etching damage on the oxide film of a base or the semiconductor substrate due to over-etching is used.
However, in the dry etching process, it becomes more difficult to control the processing dimension and detect the end point as an opening ratio of the etching mask is smaller.
Japanese Patent Application Laid-Open Publication No. 2009-152269 (Patent Document 1) describes a technique of controlling a variation of the processing dimension by correcting an etching condition depending on the opening ratio and a solid angle of a local pattern.